Jobomschrijving

Validatie engineer

Do you have Proven experience with FPGA design and verification using UVM and System Verilog and are you looking for the next step in your career?As an FPGA Design Verification Engineer, you will play a critical role in the development and verification of FPGA based hardware solutions. You will be responsible for designing, implementing, and executing test plans, as well as creating and maintaining test benches using Universal Verification Methodology (UVM) and Syste m Verilog.

Aanbod

The right candidate will be provided a challenging and varied position in a professional, high-tech environment. An appropriate salary based on your experience and education. Future prospects and excellent benefits are evident. After a period of